This invention relates in general to phase lock loops and, more particularly, to a circuit and method of reducing phase jitter in a phase lock loop.
Phase lock loops (PLL) are found in a myriad of electronic applications, such as communication receivers and clock synchronization circuits in computer systems, for providing a reference signal with a known phase for clocking incoming and out-going data. A conventional charge pump PLL comprises a phase detector for monitoring the phase difference between an input clock signal and an output signal from a voltage controlled oscillator (VCO) and generating an up control signal and a down control signal for a charge pump circuit which charges and discharges a loop filter at the input of the VCO. The up and down control signals increase and decrease the VCO output frequency, respectively, to maintain a predetermined phase relationship between signals applied to the phase detector, as is well understood.
A common problem with the conventional PLL is the occurrence of phase jitter at the output of the VCO. When the phase difference between the output signal of the VCO and the input clock signal becomes less than the resolution of the PLL, the phase detector continuously corrects the VCO for the perceived phase error. Thus, the output signal from the VCO jumps back and forth between a phase lead and phase lag with respect to the input clock signal. Such phase jitter reduces the effective bandwidth of the PLL since the output edge location of the output signal from the VCO continuously changes. The phase of the output signal of the VCO is thus only accurate within the jitter window.
Hence, what is needed is an improved phase lock loop which reduces the phase jitter of the output signal from the VCO.